hwtSimApi.basic_hdl_simulator package¶

Submodules¶

hwtSimApi.basic_hdl_simulator.io module¶

class hwtSimApi.basic_hdl_simulator.io.BasicRtlSimIo¶

Bases: object

Container of BasicRtlSimProxy objects

hwtSimApi.basic_hdl_simulator.model module¶

class hwtSimApi.basic_hdl_simulator.model.BasicRtlSimModel(sim, name=None)¶

Bases: object

Base class for model in simulator

hwtSimApi.basic_hdl_simulator.model_utils module¶

hwtSimApi.basic_hdl_simulator.model_utils.connectSimPort(sim_unit, sim_sub_unit, unit_port_name: str, sub_unit_port_name: str)¶: Connect ports of simulation models by name (Replace a child port with a parent signal/port directly)

hwtSimApi.basic_hdl_simulator.model_utils.sensitivity(proc_fn, *sensitiveTo: List[BasicRtlSimProxy | Tuple[Tuple[bool, bool], BasicRtlSimProxy]])¶: register sensitivity for process

hwtSimApi.basic_hdl_simulator.proxy module¶

class hwtSimApi.basic_hdl_simulator.proxy.BasicRtlSimProxy(sim: BasicRtlSimulator, parent, name, dtype, def_val)¶

Bases: object

Signal proxy which manages the access to a memory in simulation

Variables:

~.callbacks – list of sim processes which will be waken up if signal value is updated
~.sim – main simulator
~.name – name of property which is this proxy stored in on parent
~._name – signal name which was used in HDL
~._dtype – data type of this signal
~._origin – the object which was this proxy generated from
~._ag – agent which controls this proxy
~.parent – parent object
~.def_val – value used for initialization of value (done on sim. startup)
~.val – actual value of signal
~.val_next – place for metainformations about next update

BIT_t = <Bits3t, 1bits, unsigned>¶

callbacks¶

def_val¶

init_def_val(*args, **kwargs)¶

name¶

parent¶

read()¶

sim¶

simFallingSensProcs¶

simRisingSensProcs¶

simSensProcs¶

val¶

val_next¶

wait(cb)¶

write(val)¶

class hwtSimApi.basic_hdl_simulator.proxy.BasicRtlSimProxyArrItem(parent_proxy, item_index)¶

Bases: object

Virtual proxy for an array item of BasicRtlSimProxy

read()¶

hwtSimApi.basic_hdl_simulator.rtlSimulator module¶

class hwtSimApi.basic_hdl_simulator.rtlSimulator.BasicRtlSimulator¶

Bases: object

BEFORE_EDGE = 1¶

COMB_UPDATE_DONE = 0¶

END_OF_STEP = 2¶

bound_model(model: BasicRtlSimModel)¶

eval()¶: single simulation step

finalize()¶: flush output and clean all pending actions

reset_eval()¶: reset evaluation in COMB_UPDATE_DONE state so the comb. circuits can be evaluated again

set_trace_file(file_name, trace_depth)¶

set file where data from signals should be stored

Parameters:

file_name – name of file where trace should be stored (path of vcd file e.g.)
trace_depth – number of hyerarchy levels which should be trraced (-1 = all)

set_write_only()¶: set simulation to write only state, should be called before entering to new evaluation step

class hwtSimApi.basic_hdl_simulator.rtlSimulator.BasicRtlSimulatorSt(value)¶

Bases: Enum

An enumeration.

EVAL_COMB = 1¶

EVAL_SEQ = 2¶

PRE_SET = 0¶

hwtSimApi.basic_hdl_simulator.rtlSimulator.isEvDependentOn(sig: BasicRtlSimProxy, process) → bool¶: Check if hdl process has event dependency on signal

hwtSimApi.basic_hdl_simulator.sim_utils module¶

class hwtSimApi.basic_hdl_simulator.sim_utils.ArrayValueUpdater(nextItemVal: Value, indexes: Tuple[Value], invalidate: bool)¶: Bases: object

class hwtSimApi.basic_hdl_simulator.sim_utils.ValueUpdater(nextVal, invalidate: bool)¶: Bases: object

hwtSimApi.basic_hdl_simulator.sim_utils.sim_eval_cond(v)¶

Evaluate list of values as condition

Returns:: tuple (value, value valid)

hwtSimApi.basic_hdl_simulator.sim_utils.valueHasChanged(valA: Value, valB: Value)¶